
/******************************************************************************
* Copyright (c) 2010 - 2020 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************/

#include "xparameters.h"
#include "xycrcb2rgb.h"

/*
* The configuration table for devices
*/

XYCrCb2Rgb_Config XYCrCb2Rgb_ConfigTable[] =
{
	{
		XPAR_V_YCRCB2RGB_1_DEVICE_ID,
		XPAR_V_YCRCB2RGB_1_BASEADDR,
		XPAR_V_YCRCB2RGB_1_S_AXIS_VIDEO_FORMAT,
		XPAR_V_YCRCB2RGB_1_M_AXIS_VIDEO_FORMAT,
		XPAR_V_YCRCB2RGB_1_HAS_DEBUG,
		XPAR_V_YCRCB2RGB_1_HAS_INTC_IF,
		XPAR_V_YCRCB2RGB_1_MAX_COLS,
		XPAR_V_YCRCB2RGB_1_ACTIVE_COLS,
		XPAR_V_YCRCB2RGB_1_ACTIVE_ROWS,
		XPAR_V_YCRCB2RGB_1_MWIDTH,
		XPAR_V_YCRCB2RGB_1_COEF_RANGE,
		XPAR_V_YCRCB2RGB_1_ACOEF,
		XPAR_V_YCRCB2RGB_1_BCOEF,
		XPAR_V_YCRCB2RGB_1_CCOEF,
		XPAR_V_YCRCB2RGB_1_DCOEF,
		XPAR_V_YCRCB2RGB_1_ROFFSET,
		XPAR_V_YCRCB2RGB_1_GOFFSET,
		XPAR_V_YCRCB2RGB_1_BOFFSET,
		XPAR_V_YCRCB2RGB_1_HAS_CLIP,
		XPAR_V_YCRCB2RGB_1_HAS_CLAMP,
		XPAR_V_YCRCB2RGB_1_RGBMAX,
		XPAR_V_YCRCB2RGB_1_RGBMIN,
		XPAR_V_YCRCB2RGB_1_S_AXI_CLK_FREQ_HZ,
		XPAR_V_YCRCB2RGB_1_STANDARD_SEL,
		XPAR_V_YCRCB2RGB_1_OUTPUT_RANGE
	}
};


